I2C BUS Concept :
- The I2c bus supports any IC (Integrated Circuit) fabrication process(NMOS,CMOS,Bipolar).
- Two wires Serial Data (SDA) and Serial Clock (SCL) ,carries information between the devices connected to the bus.
- Each device is recognized by a unique address(whether it’s a micro controller,LCD Driver, memory or keyboard interface)and can operate as either a transmitter or receiver, depending on the function of the device.
- in addition to the transmitters and receivers, devices can also be considered as masters or slaves when performing data transfer.
- A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave .
Definition of I2C bus Terminology :
The Device which sends data to the bus.
The Device which receives data from the bus.
The Device which initiates a transfer, generates clock signals and terminates a transfer
The Device addressed by a master.
Multi – Master :
More than one master can attempt to control the bus at the same time with out corrupting the message.
Procedure to ensure that , if more that one master simultaneously tries to control the bus, only one is allowed to do so and the winning message is not corrupted.
Procedure to synchronize the clock signals of two or more devices.
Case Study of I2C :
The I2c is a multi-master bus. this means that more than one device capable of controlling the bus can be connected to it.
Let’s consider the case of data transfer between two micro controllers connected to the I2C bus.
this highlights the master-slave and Transmitter-receiver relationship to be found on the I2C bus.it should be noted that these relationships are not permanent,but only depend on the direction of data transfer at that time. The transfer of data would proceed as follows :
1. Suppose Micro controller A wants to send information to be micro Controller B :
- Micro controller A (Master), addresses Micro Controller B (Slave).
- Micro controller A (Master-transmitter) ,sends data to Micro controller B (Slave-receiver).
- Micro controller A terminates the transfer.
2. If micro controller A wants to receive information from micro controller B:
- Micro controller A (Master) addresses micro controller B (Slave).
- Micro controller A (Master-receiver) receives data from Micro controller B(Slave-Transmitter).
- Micro controller A terminates the transfer.
Even in this case , the Master (Micro controller A) generates the timing and terminates the transfer.
If Two or more masters try to put information onto the bus, the first to produce a ‘one’ when theother produces a ‘zero’ will lose the arbitration.
The Clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired AND connection to the SCL line.
Generation of clock signals on the I2C bus is always the responsibility of master devices . Each master generates its own clock signals when transferring data on the bus.
General Characteristics :
- Both SDA and SCL are bi-directional lines, connected to a positive supply via a current source or pull up resistor.
- When the bus is free , both lines are HIGH.
- The output stages of the devices connected to the bus must have an open drain or open collector to perform the wired AND function.
- Data on the I2C bus can be transferred at rates of upto
a. 100 kbit/s in the Standard Mode
b. 400 kbit/s in the Fast-mode.
c. 3.4Mbit/s in the High-speed Mode.
5. The number of interfaces connected to the bus solely dependent on the bus capacitance limit of 400pF.
BIT Transfer :
Due to the variety of different technology devices (CMOS, NMOS, bipolar) which can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and “1” (HIGH) are not fixed and depended on the associated level of Vdd.
One clock pulse is generated for each data bit transferred.
Data Validity :
The Data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.
START and STOP Conditions :
With in the procedure of the I2C bus, unique situations arisewhich are defined as START(S) and STOP(P)conditions.
- A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case. This situation indicates START Condition.
- A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.
Start and Stop conditions are always generated by the Master. The bus is considered to be busy after the START condition.
The bus is considered to be free again a certain time after the STOP condition.