Testing ARINC 429 Requirement (Typical) :

Req :

Software shall receive the ARINC Label 314, XY Position as defined below.

Test Approach :

• This requirement, related to communication, should be tested for:
  • Data validity in terms of valid SSM, P, SDI
  • Data value, normal and robustness
  • Data receive rate

Testing Data Bus Communication Requirement (Typical):

Req:

Software shall transmit the following ARINC Label on the Avionics bus.

• Label L1, Rate 100ms, Message Format: BNR, Data Format: ___
• Label L2, Rate 100ms, Format: Discrete, Data Format: ___
• Label L3, Rate 100ms, Format: BNR, Data Format: ___
• Label L4, Rate 100ms, Format: BNR, Data Format: ___

Test Approach :

•  Prior to coming to this requirement, it is assumed that all the labels have been tested for Message Format,
  Rate, and Data Format for normal/robustness cases. The approach here is testing for completeness.
• Test that all the messages listed in the requirement are transmitted.
• Test that no other message apart from the one listed is transmitted.

Testing Discrete Interface Requirement :

Req :

Software shall interface the Pin programming discrete from the input Pin 1

Test Approach :

• Make the Pin 1 high (either via discrete simulator or by giving the required voltage at the pin)
• Check that Software receives the discrete status as high
• Make the Pin 1 low
• Check that Software receives the discrete status as low

Testing Watchdog Requirement:

Req :

Software shall configure the external watchdog for 5 ms timeout

Test Approach :

•  Prove that SW has configured the watchdog for 5 ms, and DSP remains alive when configured
• Induce scenario that SW is unable to serve the watchdog, thus expecting the DSP reset within 5 ms

Testing Stack Requirement:

Req :

Software shall monitor the stack boundary when 70% of the stack limit is utilized by raising ‘STACK FAIL’
bit at specified memory location

Test Approach :

• Important part of test is to verify that SW can handle the failure condition when stack overflows in a
  predictable manner. Usually this is done as part of worst case timing testing.
• Assume (for approach purpose) that stack memory ranges 0x200 to 0x2000, hence 70% = 0x1700
• Assume (for approach purpose) 16 bit memory access

Testing CRC Requirement:

Req :

•  A CRC check shall be performed on the contents of the program ROM during CBIT.
• If the test detects a bad CRC, software shall stop further execution after attempting to report the failure
  over the ARINC bus, Label 310, Bit 2.

Test Approach :

• Check that no CRC error is reported on the ARINC Label 310, Bit 2
• Corrupt the CRC either by:
  • If the CRC is stored in RAM, halt the program, and corrupt the CRC using emulator
  • If there is no access to alter the CRC, rebuild the program with wrong CRC, power up
• Check that CRC error is reported on the ARINC Label 310, Bit 2
• Check any expected ‘refresh or computed’ data is no more refreshed.

Testing Timing Margin Requirement :

Req :

The software shall have 30% spare timing margin at the time of certification

Test Approach :

Note: Timer Utilization = Obtained Timing / Expected Timing where,
Expected Timing = Rate at which the main scheduler operates and,
Obtained Timing = Worst case time obtained upon driving the system to maximum utilization based on
inputs/scenarios
The guideline for maximum utilization for worst case timing should be:

• To the extent possible, SW should acquire all the inputs
• To the extent possible, SW should produce the output
• Call-tree should be analyzed to be invoked to maximum. However it should be noted that call tree can give
  the deepest nesting path on synchronous event, but asynchronous event should also be considered for
  worst timing analysis. This needs to be assessed based on the knowledge of software architecture apart
  from high level requirement.
• The timing should be usually measured by the clock different than the one used for implementing the main
  scheduler should be used. Example – timing measured via scope.
• Generally preferred method is to monitor an output line (or output signal) that will be OFF in the start of
  scheduler and ON in the end of schedule. Measured time should be OFF-OFF period in a scope.

Testing Power On Built-In-Test Requirements:

Req :

• The software shall perform the ARINC Transreceiver test during Power-up test
• The software shall transition to ‘Failed mode’ if the ARINC test fails
• The software shall transition to ‘Normal mode’ if the ARINC test passes

Test Approach :

Note: Usually all the power-up test are via software-controlled, example making the routing of RX->Tx->Rx
based on control register, and hence test case may not have provision to have any control while the
DSP/controller power’s up.

Hence possible options to test these requirements are:

• On any output communication message from SW
• Storage of ARINC status on the memory (like RAM, NVRAM etc) else,
• Go for debug based testing if allowed on the software using debugger Or,
• Modify the code to have the status of test reflected in communication output message or, memory storage.
  The modified code should be justified in terms of documentation and need or,
• Check any output that is outcome only when the SW is in normal mode under ‘Pass’ state of ARINC Test,
  and similarly check any output that is outcome only when the SW is in failed mode under ‘Fail’ state of
  ARINC Test,
  For any approach of the test being selected, test case should be written for ‘Pass’ and ‘Fail’ outcome of ARINC
  Test.

Testing Software Partitioning Requirement:

Req :

• The software shall reside in Partition A.
• The software shall interact with Partition B using communication bus/protocol xxx.
• The software shall receive the following input from Partition B ….
• The software shall transmit the following output to the Partition B ….

Test Approach :

• Review of the executable load procedure on the Partition A
• Test Case should be executed on the HSIT environment
• Test Partition to replicate the Partition B should be made to provide the data/communication interface to
  Partition A